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Features
* * * * * * * * * * * * * * * * * *
Operating Range from 5V to 18V Baud Rate from 2.6 Kbaud up to 20 Kbaud Improved Slew Rate Control According to LIN Specification 2.0 Fully Compatible with 3.3V and 5V Devices Dominant Time-out Function at Transmit Data (TXD) Normal and Sleep Mode Wake-up Capability via LIN Bus (90 s Dominant) External Wake-up via WAKE Pin (130 s Low Level) Control of External Voltage Regulator via INH Pin Very Low Standby Current During Sleep Mode (10 A) 60V Load Dump Protection at LIN Pin (42-V Power Net) Wake-up Source Recognition Bus Pin Short-circuit Protected versus GND and Battery LIN Input Current < 3 A if VBAT Is Disconnected Overtemperature Protection High EMC Level Interference and Damage Protection According to ISO/CD 7637 ESD HBM 6 kV at LIN Bus Pin and Supply VS Pin
LIN Transceiver ATA6661
1. Description
The ATA6661 is a fully integrated LIN transceiver according to the LIN specification 2.0. It interfaces the LIN protocol handler and the physical layer. The device is designed to handle the low-speed data communication in vehicles, e.g., in convenience electronics. Improved slope control at the LIN bus ensures secure data communication up to 20 kBaud with an RC-oscillator for protocol handling. In order to comply with the 42-V power net requirements, the bus output is capable of withstanding high voltages. Sleep mode guarantees minimal current consumption.
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Figure 1-1. Block Diagram
ATA6661
RXD 1 Receiver 7 VS
+
6 Filter
LIN
Wake up bus timer TXD 4 TXD Time-out timer Slew rate control
Short circuit and overtemperature protection
VS Control unit WAKE 3 Wake-up timer Standby mode
VS 5 GND
2 EN
8 INH
2. Pin Configuration
Figure 2-1. Pinning SO8
RXD EN WAKE TXD 1 2 3 4 8 7 6 5 INH VS LIN GND
Figure 2-2.
Pin 1 2 3 4 5 6 7 8
Pin Description
Symbol RXD EN WAKE TXD GND LIN VS INH Function Receive data output (open drain) Enables normal mode, when the input is open or low, the device is in sleep mode High voltage input for local wake-up request Transmit data input; active low output (strong pull-down) after a local wake-up request Ground LIN bus line input/output Battery supply Battery related inhibit output for controlling an external voltage regulator; active high after a wake-up request
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3. Functional Description
3.1 Supply Pin (VS) 3.2 Ground Pin (GND)
ATA6661
Undervoltage detection is implemented to disable transmission if VS is falling to a value below 5V to avoid false bus messages. After switching on VS the IC switches to pre-normal mode and INHIBIT is switched on. The supply current in sleep mode is typically 10 A.
The ATA6661 is neutral on the LIN pin in case of a GND disconnection. It is able to handle a ground shift up to 3V for VS > 9V.
3.3
Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown as well as an internal pull-up resistor according to LIN specification 2.0 are implemented. The voltage range is from -27V to +60V. This pin exhibits no reverse current from the LIN bus to VS, even in case of a GND shift or VBatt disconnection. The LIN receiver thresholds are compatible to the LIN protocol specification.The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope controlled. The output has a short circuit limitation. This is a self adapting current limitation; i.e., during current limitation as the chip temperature increases so the current reduces.
3.4
Input Pin (TXD)
This pin is the microcontroller interface to control the state of the LIN output. TXD is low to bring LIN low. If TXD is high, the LIN output transistor is turned off. In this case, the bus is in recessive mode via the internal pull-up resistor. The TXD pin is compatible to a 3.3V and 5V supply.
3.5
TXD Dominant Time-out Function
The TXD input has an internal pull-down resistor. An internal timer prevents the bus line from being driven permanently in dominant state. If TXD is forced low longer than tdom > 6 ms, the pin LIN will be switched off to recessive mode. To reset this mode switch TXD to high (>10 s) before switching LIN to dominant again.
3.6
Output Pin (RXD)
This pin reports to the microcontroller the state of the LIN bus. LIN high (recessive) is reported by a high level at RXD, LIN low (dominant) is reported by a low voltage at RXD. The output is an open drain, therefore, it is compatible to a 3.3V or 5V power supply. The AC characteristics are defined with a pull-up resistor of 5 k to 5V and a load capacitor of 20 pF. The output is short-current protected. In unpowered mode (VS = 0V), RXD is switched off. For ESD protection a Zener diode is implemented with VZ = 6.1V.
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3.7 Enable Input Pin (EN)
This pin controls the operation mode of the interface. If EN = 1, the interface is in normal mode, with the transmission path from TXD to LIN and from LIN to Rx both active. If EN = 0, the device is switched to sleep mode and no transmission is possible. In sleep mode, the LIN bus pin is connected to VS with a weak pull-up current source. The device can transmit only after being woken up (see next section "Inhibit Output Pin (INH)" ). During sleep mode the device is still supplied from the battery voltage. The supply current is typically 10 A. The pin EN provides a pull-down resistor in order to force the transceiver into sleep mode in case the pin is disconnected.
3.8
Inhibit Output Pin (INH)
This pin is used to control an external switchable voltage regulator having a wake-up input. The inhibit pin provides an internal switch towards pin VS. If the device is in normal mode, the inhibit high-side switch is turned on and the external voltage regulator is activated. When the device is in sleep mode, the inhibit switch is turned off and disables the voltage regulator. A wake-up event on the LIN bus or at pin WAKE will switch the INH pin to the VS level. After a system power-up (VS rises from zero), the pin INH switches automatically to the VS level. The RDSon of the high-side output is < 1 k.
3.9
Wake-up Input Pin (WAKE)
This pin is a high-voltage input used to wake-up the device from sleep mode. It is usually connected to an external switch in the application to generate a local wake-up. If you do not need a local wake-up in your application, connect pin WAKE directly to pin VS. A pull-up current source with typically -10 A is implemented. The voltage threshold for a wake-up signal is 3V below the VS voltage with an output current of typical -3 A. Wake-up events from sleep mode: * LIN bus * EN pin * WAKE pin Figure 3-1 on page 6, Figure 3-2 and Figure 3-3 on page 7 show details of wake-up operations.
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3.10 Mode of Operation
ATA6661
1. Normal mode This is the normal transmitting and receiving mode. All features are available. 2. Sleep mode In this mode the transmission path is disabled and the device is in low power mode. Supply current from VBatt is typically 10 A. A wake-up signal from the LIN bus or via pin WAKE will be detected and switches the device to pre-normal mode. If EN, then switches to high, normal mode is activated. Input debounce timers at pin WAKE (TWAKE), LIN (TBUS) and EN (Tsleep,Tnom) prevent unwanted wake-up events due to automotive transients or EMI. In sleep mode the INH pin is floating. The internal termination between pin LIN and pin VS is disabled to minimize the power dissipation in case pin LIN is short-circuited to GND. Only a weak pull-up current (typical 10 A) between pin LIN and pin VS is present. 3. Pre-normal mode At system power-up, the device automatically switches to pre-normal mode. It switches the INH pin to a high state, to the VS level. The microcontroller of the application will then confirm the normal mode by setting the EN pin to high. 4. Unpowered mode In this mode the LIN transceiver is disabled. Data communication is switched off. If VS is higher than VSth undervoltage threshold, the IC mode change from Unpowered to Pre-normal mode.
3.11
Remote Wake-up via Dominant Bus State
A falling edge at pin LIN, followed by a dominant bus level maintained for a certain time period (TBUS), results in a remote wake-up request. The device switches to pre-normal mode. Pin INH is activated (switches to V S ) and the internal termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller (see Figure 3-2 on page 7). The voltage threshold for a wake-up signal is 3V below the VS voltage with an output current of typical -3 A.
3.12
Local Wake-up via Pin WAKE
A falling edge at pin WAKE, followed by a low level maintained for a certain time period (TWAKE), results in a local wake-up request. The extra long wake-up time (TWAKE) ensures that no transient, according to ISO7637, creates a wake-up. The device switches to pre-normal mode. Pin INH is activated (switches to VS) and the internal termination resistor is switched on. The local wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller and a strong pull-down at pin TXD (see Figure 3-3 on page 7).
3.13
Wake-up Source Recognition
The device can distinguish between a local wake-up request (pin WAKE) and a remote wake-up request (dominant LIN bus). The wake-up source can be read on pin TXD in pre-normal mode. If an external pull-up resistor (typically 5 k) on pin TXD to the power supply of the microcontroller has been added, a high level indicates a remote wake-up request (weak pull-down at pin TXD) and a low level indicates a local wake-up request (strong pull-down at pin TXD). The wake-up request flag (signalled on pin RXD) as well as the wake-up source flag (signalled on pin TXD) are reset immediately, if the microcontroller sets pin EN to high (see Figure 3-2 on page 7 and Figure 3-3).
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Figure 3-1. Mode of Operation
Unpowered Mode VBatt = 0V b a a: VS > 5V b: VS < 4V c: Bus wake-up event d: Wake-up from Wake switch Pre-normal Mode b INH: high (INH internal High Side switch ON) Communication: OFF b c
EN = 1
Go to sleep command
d
EN = 0 Normal Mode INH: high (INH HS switch ON) Communication: ON
Local wake-up event
Sleep Mode EN = 1 INH: high impedance (INH HS switch OFF) Communication: OFF
3.14
Fail-safe Features
* There are now reverse currents < 3 A at pin LIN during loss of VBAT or GND. Optimal behavior for bus systems where some slave nodes supplied from battery or ignition. * Pin EN provides pull-down resistor to force the transceiver into sleep mode if EN is disconnected. * Pin RXD is set floating if VBAT is disconnected. * Pin TXD provides a pull-down resistor to provide a static low if TXD is disconnected. * The LIN output driver has a current limitation and if the junction temperature Tj exceeds the thermal shut-down temperature Toff the output driver switches off. * The implemented hysteresis Thys enables the LIN output again after the temperature has been decreased.
3.15
Physical Layer Compatibility
Since the LIN physical layer is independent from higher LIN layers (e.g. LIN protocol layer), all nodes with a LIN physical layer according to this revision can be mixed with LIN physical layer nodes, which are according to older versions (i.e. LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), without any restrictions. A higher ratio of nodes according to this LIN physical layer specification or the one of revision 2.0 will result in a higher transmission reliability.
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Figure 3-2. LIN Wake-up Waveform Diagram
LIN bus INH Low or floating High RXD High or floating Bus wake-up filtering time TBus External voltage regulator On state Off state Node in Operation EN High Low
ATA6661
Regulator wake-up time delay EN Node in sleep state Microcontroller start-up time delay
Figure 3-3.
LIN Wake-up from Wake-up Switch
Wake pin State change
INH
Low or floating
High
RXD
High or floating
Low
High weak pull-down
TXD
TXD weak pull-down resistor Wake filtering time TWAKE
TXD strong pull-down
Voltage regulator
On state Off state Node in Operation EN High
Regulator wake-up time delay EN Node in sleep state Microcontroller start-up time delay
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4. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters VS - Continuous supply voltage Wake DC and transient voltage (with 33 k serial resistor) - Transient voltage due to ISO7637 (coupling 1 nF) Logic pins (RXD, TXD, EN) LIN - DC voltage - Transient voltage due to ISO7637 (coupling 1 nF) INH - DC voltage ESD (DIN EN 61000-4-2) According LIN EMC Test Specification V1.3 - Pin VS, LIN - Pin Wake (with 33 k serial resistor) ESD S5.1 - All pins CDM ESD STM 5.3.1-1999 - All pins FCDM ESD STM 5.3.1- All pins MM JEDEC A115A - All pins Junction temperature Storage temperature Operating ambient temperature Thermal shutdown Thermal shutdown hysteresis Tj Tstg Tamb Toff Thys Symbol Min. -0.3 -40 -150 -0.3 -40 -150 -0.3 Typ. Max. +40 +40 +100 +6 +60 +100 +40 Unit V V V V V V V
-6000 -5000 -3000 -500 -1000 -200 -40 -55 -40 150 5 165 10
+6000 +5000 +3000 +500 +1000 +200 +150 +150 +125 180 20
V V V V V V C C C C C
5. Thermal Resistance
Parameters Thermal resistance junction ambient Symbol RthJA Value 160 Unit K/W
8
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6. Electrical Characteristics
5V < VS < 18V, Tamb = -40C to +125C No. 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.1 2.2 2.3 2.4 3 3.1 3.2 3.3 3.4 3.5 4 4.1 4.2 4.3 4.4 4.5 5 5.1 5.2 6 6.1 6.2 Supply current in normal mode VS undervoltage threshold VS undervoltage threshold hysteresis RXD Output Pin (Open Drain) Low level input current RXD saturation voltage High level leakage current ESD zener diode TXD Input Pin Low level voltage input High level voltage input Pull-down resistor Low level leakage current Low-level input current at local wake-up request EN Input Pin Low level voltage input High level voltage input Pull-down resistor Low level input current Enable negative slope for go to sleep INH Output Pin High level voltage High level leakage current WAKE Pin High level input voltage Low level input voltage IWAKE = Typically -3 A 3 3 VWAKEH VWAKEL VS - 1V -27V Normal mode IINH = -200 A Sleep mode VINH = 27V, VBatt = 27V 8 8 VINHH IINHL VS - 0.8 -3 VS +3 VEN = 5V VEN = 0V Negative slope VEN = 2V to 0.8V 2 2 2 2 2 VENL VENH REN IEN SlopeEN -0.3 2 125 -3 250 VTXD = 5V VTXD = 0V Pre-normal mode VLIN = VBAT; VWAKE = 0V 4 4 4 4 4 VTXDL VTXDH RTXD ITXD ITXDwake -0.3 2 125 -3 2 5 250 Normal mode VLIN = 0V, VRXD = 0.4V 5 k pull-up resistor to 5V Normal mode VLIN = VBAT, VRXD = 5V IRXD = 100 A 1 1 1 1 IRXDL VsatRXD IRXDH VZRXD -3 6.1 2 5 8 0.4 +3 8.6 7 Parameters VS Pin Nominal DC voltage range Supply current in sleep mode Sleep mode Vlin > VBatt - 0.5V VBatt < 14V Bus recessive Bus dominant Total bus load > 500 7 7 7 7 VS IVSstby IVSrec IVSdom VSth VSth_hys 4 5 13.5 10 1.6 1.6 4.6 0.2 18 20 3 3 5 Test Conditions Pin Symbol Min. Typ.
ATA6661
Max.
Unit V A mA mA V V
Type* A A A A A A
mA V A V V V k A mA
A A A A A A A A A
+0.8 7 600 +3 8
+0.8 7 600 +3 60
V V k A s
A A A A A
V A
A A
VS + 0.3V VS - 3V
V V
A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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6. Electrical Characteristics (Continued)
5V < VS < 18V, Tamb = -40C to +125C No. 6.3 6.4 7 7.1 7.2 7.3 7.4 7.5 7.6 Parameters Wake pull-up current High level leakage current LIN Bus Driver Driver recessive output voltage Driver dominant voltage VBUSdom_DRV_LoSUP Driver dominant voltage VBUSdom_DRV_HiSUP Driver dominant voltage VBUSdom_DRV_LoSUP Driver dominant voltage VBUSdom_DRV_HiSUP Pull-up resistor to VS Self-adapting current limitation VBUS = VBAT_max Input leakage current at the receiver, inclusive pull-up resistor as specified RLOAD = 500/1 k VVS = 7V, Rload = 500 VVS = 18V, Rload = 500 VVS = 7V, Rload = 1000 VVS = 18V, Rload = 1000 The serial diode is mandatory Tj = 125C Tj = 27C Tj = -40C Input leakage current Driver off VBUS = 0V, VBatt = 12V Driver off 8V < VBAT < 18V 8V < VBUS < 18V VBUS VBAT 6 6 6 6 6 6 VBUSrec V_LoSUP V_HiSUP V_LoSUP_1k V_HiSUP_1k_ RLIN IBUS_LIM 0.6 0.8 20 52 100 150 -1 30 60 110 170 230 0.9 x VS VS 1.2 2 V V V V V k mA mA mA mA A A A A A A Test Conditions VS < 27V VS = 27V, VWAKE = 27V Pin 3 3 Symbol IWAKE IWAKE Min. -30 -5 Typ. -10 +5 Max. Unit A A Type* A A
7.7
6
A
7.8
6
IBUS_PAS_dom
A
7.9
Leakage current LIN recessive
6
IBUS_PAS_rec
15
20
A
A
7.10
Leakage current at ground loss, Control unit disconnected from GNDDevice = VS ground, VBAT =12V Loss of local ground must not 0V < VBUS < 18V affect communication in the residual network Node has to sustain the current that can flow under this condition, bus must remain operational under this condition LIN Bus Receiver Center of receiver threshold Receiver dominant state Receiver recessive state Receiver input hysteresis Wake detection LIN High level input voltage VBUS_CNT = (Vth_dom + Vth_rec)/2 VEN = 5V VEN = 5V VHYS = Vth_rec - Vth_dom VBAT disconnected VSUP_Device = GND 0V < VBUS < 18V
6
IBUS_NO_gnd
-10
+0.5
+10
A
A
7.11
6
IBUS
0.5
3
A
A
8 8.1 8.2 8.3 8.4 8.5
6 6 6 6 6
VBUS_CNT VBUSdom VBUSrec VBUShys VLINH
0.475 x VS -27 0.6 x VS 0.028 x VS VS - 1V
0.5 x VS
0.525 x VS 0.4 x VS 40
V V V V V
A A A A A
0.1 x VS
0.175 x VS VS + 0.3V
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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6. Electrical Characteristics (Continued)
5V < VS < 18V, Tamb = -40C to +125C No. 8.6 8.7 9 9.1 9.2 Parameters Wake detection LIN Low level input voltage LIN pull-up current Internal Timers Dominant time for wake-up via LIN bus Time of low pulse for wake-up via pin WAKE VLIN = 0V VWAKE = 0V 6 3 TBUS TWAKE Tnorm 30 60 90 130 Test Conditions ILIN = Typically -3 A VS < 27V Pin 6 6 Symbol VLINL ILIN Min. -27V -30 -10 Typ.
ATA6661
Max. VS - 3V
Unit V A
Type* A A
150 200
s s
A A
9.3
Time delay for mode change from pre-normal mode to normal VEN = 5V mode via pin EN Time delay for mode change from normal mode into sleep mode via pin EN TXD dominant time out timer Power-up delay between VS = 5V until INH switches to high VEN = 0V VTXD = 0V VVS = 5V
2
2
10
15
s
A
9.4 9.5 9.6
2 4
Tsleep Tdom TVS
2 6
10 9
12 20 200
s ms s
A A A
10
LIN Bus Driver (see Figure 6-1 on page 12) Bus load conditions: Load1 small 1 nF 1 k, Load2 big 10 nF 500, RRXD = 5 k, CRXD = 20 pF; The following two rows specifies the timing parameters for proper operation at 20.0 Kbit/s. THRec(max) = 0.744 x VS THDom(max) = 0.581 x VS VS = 7.0V to 18V tBit = 50 s D1 = tbus_rec(min)/(2 x tBit) THRec(min) = 0.422 x VS THDom(min) = 0.284 x VS VS = 7.0V to 18V tBit = 50 s D2 = tbus_rec(max)/(2 x tBit) Load1/Load2 VS = 7.3V to 18V VS = 7.3V tsym = tSlope_fall - tSlope_rise
10.1
Duty cycle 1
6
D1
0.396
A
10.2
Duty cycle 1
6
D2
0.581
A
10.3 10.4 11 11.1
Slope time falling and rising edge at LIN Symmetry of rising and falling edge
6
tSlope_fall tSlope_rise tsym
3.5 -4
22.5 +4
s s
A A
Receiver Electrical AC Parameters of the LIN Physical Layer LIN receiver, RXD load conditions (CRXD): 20 pF, Rpull-up = 5 k Propagation delay of receiver (see Figure 6-1 on page 12) Symmetry of receiver propagation delay rising edge minus falling edge trec_pd = max(trx_pdr, trx_pdf) trx_sym = trx_pdr - trx_pdf trx_pd trx_sym -2 6 s A
11.2
+2
s
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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Figure 6-1. Definition of Bus Timing Parameter
tBit TXD (Input to transmitting node) tBit tBit tBus_dom(max) tBus_rec(min) THRec(max) VS (Transceiver supply of transmitting node) THDom(max) LIN Bus Signal Thresholds of THRec(min) THDom(min) receiving node2 Thresholds of receiving node1
tBus_dom(min)
tBus_rec(max)
RXD (Output of receiving node1) trx_pdf(1) trx_pdr(1)
RXD (Output of receiving node2) trx_pdr(2) trx_pdf(2)
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Figure 6-2.
VBATTERY + 22 F 100 nF 12V 5V +
ATA6661
Application Circuit
Master node pull-up
1k 7 VS 1 LIN sub bus Filter 6 LIN Short circuit and overtemperature protection 220 pF VS 5 GND 2 EN 8 INH Receiver
VDD Microcontroller
RXD
SCI
5 k
ATA6661
Wake-up bus timer 4 TXD IO VS 10 k 33 k External switch WAKE 3 Wake-up timer TXD Time-out timer Slew rate control
Control unit Standby mode
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7. Ordering Information
Extended Type Number ATA6661-TAQJ ATA6661-TAPJ Package SO8 SO8 Remarks LIN transceiver, Pb-free, taped and reeled LIN transceiver, Pb-free, taped and reeled
8. Package Information
Package SO8
Dimensions in mm
5.00 4.85 1.4 0.4 1.27 3.81 8 5 0.25 0.10 0.2 3.8 6.15 5.85 5.2 4.8 3.7
technical drawings according to DIN specifications
1
4
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9. Revision History
Revision No. 4729I-AUTO-12/06
ATA6661
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. History * Put datasheet in a new template * Section 3.5 "TXD Dominant Time-out Function" changed * Section 7 "Ordering Information" on page 14 changed * Put datasheet in a new template * Pb-free logo on page 1 deleted * Features on page 1 changed * Section 3-10 "Mode of Operation" on page 5 changed * Figure 3-1 "Mode of Operation" on page 6 changed * Section 3.15 "Physical Layer Compatibility" on page 6 added * Section 6 "Electrical Characteristics" number 4.5 on page 9 added * Section 6 "Electrical Characteristics" number 9.5 on page 11 changed * Section 6 "Electrical Characteristics" number 10.3 and 10.4 on page 11 added
4729H-AUTO-10/06
* Figure 6-2 "Application Circuit" on page 12 changed
4729G-AUTO-10/05 * Pb-free Logo on page 1 added
* Table "Ordering Information" on page 13 changed
* * * * * * * * * * * * * * * * * * * * * Section 2.14 "Fail-safe Features" on page 5 changed Figure 2.2 "LIN Wake-up Waveform Diagram" on page 6 changed Table "Absolute Maximum Ratings" on page 7 changed Table "Electrical Characteristics": Rows: 7.1, 7.2, 7.4, 8.5, 9.3 and 9.5 changed Put datasheet in a new template Table "Ordering Information" on page 13 changed Put datasheet into new template Section "Features" on page 1 changed Figure 1 "Block Diagram" on page 1 changed Section "Bus Pin (LIN)" on page 2 changed Section "TX Dominant Time-out Function" on page 3 changed Section "Output Pin (RXD)" on page 3 changed Section "Inhibit Output Pin (INH)" on page 3 changed Section "Wake-up Input Pin (WAKE)" on page 3 changed Section "Remote Wake-up via Dominant Bus State" on page 4 changed Section "Fail-safe Features" added Table "Absolute Maximum Ratings" on page 7 changed Table "Electrical Characteristics": Rows: 1.3, 1.4, 1.5, 6.2, 7.9, 7.10, 7.11 and 9.3 changed Table "Electrical Characteristics": Rows: 2.4, 8.5, 8.6 and 8.7 Figure 7 "Application Circuit" on page 12 changed Table "Ordering Information" on page 13 changed
4729F-AUTO-05/05
4729E-AUTO-01/05
4729D-AUTO-10/04
4729C-AUTO-06/04
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DRAFT
4729I-AUTO-12/06

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